A typical example of circuits in the field of the invention is that of a voltage regulator for reading word lines from multi-level non-volatile memories, where a precisely regulated voltage is vital to optimal reading conditions.
FIG. 1 of the drawings shows a word-line read circuit 10 in a storage device. Upon connection of a capacitor C.sub.s 12, to an output OUT of a regulator 20, a regulator output voltage V.sub.reg, which has a normal rating value of V.sub.R, falls by reason of the charge sharing effect that occurs between the total capacitive load C.sub.r 14, connected to the regulator output and the capacitor C.sub.s 12. In FIG. 1, the circuit connection is represented by a switch SW 16, which is closed when C.sub.r 14 is to be connected to the regulator output OUT.
This fall in the regulator output voltage V.sub.reg occurs very rapidly and may be excessive in the sense that it may bring the value of the voltage V.sub.reg outside its set range. The return to the voltage V.sub.reg should be sufficiently fast, i.e., the regulator output voltage must be quickly brought back into its set range.
Typical values for a storage device parameters may be:
V.sub.R =6V PA1 C.sub.r =100 pF PA1 C.sub.s =3 pF PA1 .DELTA.V.sub.max =50 mV, PA1 where, .DELTA.V.sub.max is the maximum admitted deviation of V.sub.reg from its rating value V.sub.R. In other words, the voltage V.sub.reg is judged to have been re-established, following connection to the capacitor C.sub.s, once the voltage is brought back to within 50 mV of the rating value of V.sub.reg, and subsequently held within 50 mV of that value.
The appearance of a high capacitive load value delays the regulator 20 operation in that it slows down the re-establishment of the output voltage V.sub.reg on the occurrence of charge sharing due to the previously discharged capacitor C.sub.s 12 having been connected to the voltage regulator output OUT. The amount of charge drawn by the capacitor C.sub.s 12 upon connection is: ##EQU1##
Suppose that the re-establishment time is not to exceed 20 ns, then the current that the regulator 20 is to deliver for peak efficiency would be (17.85 pC)/(20 ns) 892.5 .mu.A, assuming for simplicity that the process of re-establishing the output voltage is taking place at a constant current. Actually, this is not exactly the case, and the overall capacitive load would be charged with a decreasing current over time, so that the peak current supplied by the regulator 20 is bound to exceed the above value.
A prior solution provided a regulator for storage devices which was basically in the form of an operational amplifier 40 connected in a negative feedback loop.
This loop comprised, as shown in FIG. 2, a first stage consisting of a differential amplifier 42, and a second stage consisting of a pull-up element 44 formed of a PMOS transistor and a pull-down element or resistor divider 46 formed of two resistors R.sub.1 48, and R.sub.2 52. The combined stages form the operational amplifier 40. The inverting terminal of the differential amplifier 42 is applied a precise constant voltage, designated V.sub.BG in FIG. 2. A junction node 50 between the resistors R.sub.1 48 and R.sub.2 52 is connected to a non-inverting input of the differential amplifier 42, thereby closing the negative feedback loop. In order to provide the loop with adequate stability, a compensation network 54, represented by a block COMP in FIG. 2, may consist of a capacitor connected between the gate and the drain of the pull-up PMOS transistor 44 in the second stage. Other compensation networks may be used, however, such as that discussed by D. B. Ribner and M. A. Copeland in an article "Design Techniques for Cascoded CMOS Op Amps with Improved PSRR and Common-mode Input Range", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, December 1984, pages 919-925.
If the loop gain of the feedback loop is sufficiently high, barring such inaccuracies as offset voltages, then the regulator output voltage V.sub.R in the steady-state condition is given as V.sub.R =V.sub.BG *(1+R.sub.1 /R.sub.2). In an integrated circuit, the resistance ratio between two resistors can be provided with great precision, but for less-than-ideal effects, and the accuracy in value of V.sub.R will depend essentially on the accuracy achieved for the voltage V.sub.BG. The latter accuracy can be obtained by means of a band-gap type of voltage reference generator, which is known to generate a fairly precise and stable voltage even with such varying factors as the supply voltage and temperature.
Upon connection of the capacitor C.sub.s 12 to the regulator 40 output, the charge originally stored into the capacitor C.sub.r 14 becomes shared with the capacitor C.sub.s. The regulator output voltage at the end of the charge sharing process is, assuming inaction of the control loop at this stage: EQU V.sub.reg =C.sub.s V.sub.R /(C.sub.s +C.sub.r) (1)
Therefore, the theoretical voltage drop at the regulator output can be written as: EQU .DELTA.V.sub.reg =V.sub.r /(1+C.sub.r /C.sub.s)=V.sub.R C.sub.s /C.sub.r (2)
Substituting the values given above, we get .DELTA.V.sub.r =180 mV, which exceeds the maximum error value admitted on line V.sub.reg (.DELTA.V.sub.max =50 mV). Thus, the regulator 40 is to supply the required electric charge for re-establishing the voltage to its desired value.
With very high total capacitive loads (e.g., 100 pF) on the regulator 40 output, the voltage V.sub.reg may not be re-established as quickly as desired, because the product of band by gain is limited in the amplifying structure.
Prior approaches to solving this problem presupposed that the capacitance of C.sub.s 12, and the time when its connection to the regulator output node OUT is required, were known beforehand. In addition, such approaches involved of necessity the generation of appropriate clock drive signals.
However, such prior solutions cannot be used where the capacitance of C.sub.s 12 or the time when C.sub.s is connected to the regulator output node OUT is not exactly known beforehand (as is the case when the problem is unrelated to the drive of word lines in a non-volatile memory).
Until now, no circuit solution was available that provides for fast re-establishment of the voltage V.sub.reg upon a previously discharged capacitor being connected to the output terminal of the regulator, through the use of a circuit that is easy to implement, and not the prior capacitive compensation or capacitive boost techniques.